T 1849/08 - Drawn To Scale

This appeal was filed against the refusal of an application by the competent Examining Division (ED).

Claim 1 of the main request read:

A semiconductor device comprising

a semiconductor substrate having a pair of main surfaces;

a first semiconductor region (10) of first conductivity-type located in the substrate;

a second semiconductor region (22) of second conductivity-type located on the first semiconductor region;

plural third semiconductor regions (23) of second conductivity-type having carrier density higher than carrier density of the second semiconductor region (22);

a fourth semiconductor region (31) of first conductivity-type located in the third semiconductor region;

a fifth semiconductor region (40) of second conductivity-type located in the fourth semiconductor region (31);

a gate insulation film (52) formed on surfaces of the second, third, fourth and fifth semiconductor regions;

a gate electrode (3) formed on the gate insulation films;

an emitter electrode (2) contacting with low resistance to the fourth semiconductor region (31) and the fifth semiconductor region (40); and

a collector electrode (1) contacting with low resistance to the first (10) semiconductor region,

characterised in that the sheet carrier density of the third semiconductor region (23) is 1 x 10**(12) cm**(-2) or less.

The applicant did not agree with what the ED considered to be disclosed in document D1.

Here is what the Board had to say on that matter:

[2.1.1] Document D1 discloses an Insulated Gate Bipolar Transistor (IGBT) wherein the body regions are enclosed within respective enhancement regions of the same conductivity type as the (underlying) lightly doped drain regions, but more heavily doped (cf. figures 1 and 2 with corresponding description).

In particular, D1 discloses, in the terms of claim 1 of the appellant’s main request, a semiconductor device comprising:

a semiconductor substrate having a pair of main surfaces;

a first semiconductor region (2) of first conductivity-type (e.g. p-type) (cf. page 3, lines 16 to 18) located in the substrate;

a second semiconductor region (1) of second conductivity-type (n-type) located on the first semiconductor region;

plural third semiconductor regions (12) of second conductivity-type (n-type) having carrier density higher than carrier density of the second semiconductor region (cf. page 3, lines 23 to 28; figures 1 and 2);

a fourth semiconductor region (4, 5) of first conductivity-type (p-type) located in the third semiconductor region;

a fifth semiconductor region (6) of second conductivity-type (n-type) located in the fourth semiconductor region (4);

a gate insulation film (8) formed on surfaces of the second, third, fourth and fifth semiconductor regions;

a gate electrode (7) formed on the gate insulation films;

an emitter electrode (10) contacting with low resistance to the fourth semiconductor region (4) and the fifth semiconductor region (6); and

a collector electrode (11) contacting with low resistance to the first (2) semiconductor region.

[2.1.2] Contested by the appellant is whether in D1 the third semiconductor region (12) has a sheet carrier density of 1 x 10**(12) cm**(-2)or less.

According to D1 

“Figure 2 is a diagram (not to scale), showing the doping concentration profiles (expressed in log. atoms (at) per cubic centimeter) of the various doped semiconductor regions of the structure of Figure 1, as a function of the distance x from the semiconductor surface” (page 3, lines 24 to 26).

The appellant argued that since the figure 2 diagram was stated to be “not to scale”, the diagram only provided an indication of the relative dopant concentrations of the various regions of the structure, but no information could be derived from the diagram on any concrete dopant value or thickness of any of the regions. Accordingly, the sheet carrier density of the third semiconductor region (12) as defined in claim 1 could not be derived from the diagram. As document D1 did not disclose any value for the sheet carrier density of the third semiconductor region (12) anywhere else in the document, this feature was not disclosed in D1 and therefore the subject-matter of claim 1 was new over D1.

[2.1.3] Decisive for the information content of a prior art document is what a person skilled in the art reading the document would understand from it.

Although in the passage of the description of D1 referred to above by the appellant the diagram of figure 2 is indicated to be “not to scale”, the diagram is actually provided with a scale both on the horizontal and the vertical axis, providing, as stated in the description, the doping concentration profiles expressed in atoms/cm**(3) in logarithmic scale of the various doped semiconductor regions of the structure of figure 1, as a function of the distance x from the semiconductor surface in microns (cf. page 3, lines 24 to 26). The vertical axis of the diagram of figure 2 is as a matter of fact provided with the decades of the logarithmic scale, whereby the indicated scale is also clearly consistent with the plotted value of 2.10**(14) cm**(-2) corresponding to the dopant concentration of the semiconductor layer 1 provided in the description (cf. page 3, lines 45 to 48). Hence, to a person skilled in the art the diagram of figure 2 is to scale.

The description also at no other point provides any indication that, or indeed in which respect, the diagram of figure 2 would in fact not be to scale. According to the only other, formal, explicit reference to the nature of figure 2 in D1, “Figure 2 is a diagram showing the doping concentration profiles of some doped semiconductor regions of the structure of Figure 1” (page 2, lines 58 to 59), no mention being made of the diagram not being to scale.

In summary, there is nothing to a person skilled in the art in figure 2 itself or in the rest of document D1 supporting the above isolated statement in brackets that the diagram of figure 2 would be “not to scale”. The skilled reader would, thus, consider this statement to be made in error and disregard it.

Accordingly, in the board’s judgement the skilled reader would understand figure 2 of D1 to show the doping concentration in atoms/cm**(3) in logarithmic scale, with the decades being indicated on the vertical axis, as a function of the distance from the semiconductor surface in microns.

[2.1.4] As region 1 has a dopant concentration of 2.10**(14) atoms/cm**(3), it is shown in figure 2 that region 12 has a dopant concentration of less than about 4.10**(15) atoms/cm**(3) and a thickness of about 1.3 mym. This yields a sheet carrier density of less then 5.2.10**(11) cm**(-2) for region 12. This falls well within the claimed range of 1 x 10**(12) cm**(-2) or less.

Furthermore, factors, addressed in the decision under appeal […], such as the assumption of thermal activation of all dopants, the box profile approximation using the highest dopant concentration of region 12 as shown in figure 2, and neglecting any dopant compensation by p-type dopants present in region 12 (see figure 2), all result in the above indicated value of 5.2.10**(11) cm**(-2)being an overestimation of the actual sheet carrier density of region 12.

Accordingly, the subject-matter of claim 1 according to the main request is not new over document D1 (A 54(1) and (2) EPC 1973).

Therefore, the appellant’s main request is not allowable.

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